CA-Santa Clara, Job Title: Senior Logic Design Engineer Location: Santa Clara, CA (Hybrid, 3 days onsite) Duration: 12 Months JOB: 1. Work on IP/Block logic design includes but not limited to: System RAS, Memory ECC, and interface logic designs. 2. Communicate with architects and external IP teams. Design MAS work as needed. 3. Support on going formal verification on design set up and optimization independently.